1. Field of the Invention
The invention relates to a drain voltage limiter designed for a low-capacity, erasable, electrically programmable MOS memory that works at high speed in reading mode.
2. Description of the Prior Art
Electrically programmable memory cells are constituted by a floating gate transistor with its control gate connected to a word line, its drain connected to a bit line and its source connected to a reference potential that is generally the electrical ground of the circuit.
The cells are organized in matrix form: the transistors (or memory cells) are arranged in rows and columns. The transistors of a given row have their control gates connected to one and the same word line, and the transistors of a given column have their drains connected to one and the same bit line. A memory cell is addressed through the addressing of a bit line and a word line.
The programming or erasure of a memory cell consists in the injection of electrical charges into the floating gate, or in making them leave the floating gate, by the application, for example, of high potentials, erasure by ultraviolet rays, etc. These are well known methods.
The quantity of charges stored at the floating gate determines the threshold voltage Vs of the transistor: in terms of absolute value, this is the minimum voltage that must be applied between the gate and the source for the cell to become conductive. For an N channel transistor, for example, a threshold voltage for an erased state may be two volts and a threshold voltage for a programmed state may be eight volts. Thus, if a reading voltage of the order of five volts is applied between the source and the drain, the cell conducts a current of about a hundred microamperes if it is erased, and it is not conductive if it is programmed.
The current conducted by the cell is very low. Hence, to read the state of the cell, there has to be a current/voltage conversion. In a simple, well-known structure, the bit line is pre-loaded by a current generator which takes the drain to a potential close to Vcc. The current generator will conventionally be formed by a resistive transistor with zero threshold voltage, the gate and the source of this transistor being short-circuited. When a reading voltage is applied between the source and the gate of the cell, if the cell is conductive it will make its drain tend towards 0 volts. If it is not conductive, the drain remains at the same pre-loading voltage, close to Vcc. A reading amplifier, centered on a detection threshold ranging from 0 to 5 volts, may then detect an erased state or a programmed state.
Because of the matrix organization of the memories, the bit lines, which have many cells and are all connected to the reading amplifier, are highly capacitive: in parallel, at the drain and the source (grounded), it is possible to represent the equivalent capacitance. The cell, for its part is highly resistive: the current that flows is very low. It follows therefrom that it takes very long for the data of a memory cell to be set up on the bit line. This is so above all if it is necessary to read a state opposite the one pre-positioned on the bit line, i.e. an erased state while the bit line is pre-positioned in a programmed state by the pre-load circuit (current generator).
Furthermore, the drain of the cell undergoes major variations in voltage: for example, when the cell is in an erased state, its drain pre-positioned at Vcc goes to 0 volts when is being read. Repeated reading operations then tend to modify the quantity of charges stored at the floating gate; the cell tends to be programmed. Its lifetime becomes shorter. This is a phenomenon of stress of the cell. It is particularly pronounced when the gate lengths are small (submicron).
Hence, a circuit has been introduced between the bit line and the drain of the cell. This circuit has the function of absorbing the difference in voltage prompted by the reading of an erased state, the bit line being pre-positioned for a programmed state: the potential of the drain of the memory cell varies to a far smaller extent. This circuit for limiting the voltage variation of the drain is, in a known way, formed by a transistor that shall be called a compensation transistor, series connected between the bit line and the drain of the memory cell. The source of this transistor is therefore connected to the drain of the cell. This source is also the input of a follower-inverter the output of which is connected to the gate of the compensation transistor. The drain of the compensation transistor is connected to the input of the reading circuit and to the output of the pre-load circuit.
This compensation transistor is more resistive than the memory cell, but is less so than the pre-load transistor.
Thus, if the cell is in an erased state and if the reading voltage is applied to its gate, the current of the cell becomes high and tends to make its drain voltage Vd diminish. Because of the follower-inverter, the gate voltage of the compensation transistor, for its part, becomes greater: this transistor is increasingly conductive, equivalent to a short-circuit.
By contrast, if the cell is in a programmed state, it becomes highly resistive. Since the compensation transistor is more resistive, and because of the inverter, the compensation transistor becomes highly resistive, more so than the cell, and takes the voltage difference at its terminals: Vd therefore undergoes very little variation.
However, while the stress effect has thus been limited, the problem of access time in reading mode, which is lengthy because of the capacity, is not resolved for all that even if, since the voltage variation is smaller, the access time is also shorter (CdV=idt).
An object of the invention is the use of an assembly such as this, with compensation transistor, for a small number of cells, in order to have a memory that is very fast in reading mode. The capacitance induced is smaller, for there are fewer cells. However, it is then the transmission time of the inverter that will hamper fast switching-over: the compensation does not follow and, in practice, there are voltage peaks on the drain, for the induced capacitance is too low. Thus, using the known approach, the problem of stress of the cell is encountered again.